1. Field of Invention
The present invention relates to a delay circuit. More particularly, the present invention relates to a delay circuit capable of self-compensation.
2. Description of Related Art
Traditional delay circuits are mainly classified into two categories: digital controlled charging delay circuits and current charging delay circuits. FIG. 1 depicts a traditional circuit schematic diagram of a digital controlled charging delay circuit. An oscillator 10 periodically generates an oscillation signal Sclk to control turning-on and turning-off of a charging switch SW. The charging switch SW is connected to a charging current source 10 and a delay capacitor Cs. The charging current source 10 is connected to a driving voltage Vdd. A description is provided with reference to FIG. 1 and FIG. 2. FIG. 2 is waveform diagrams of an oscillation signal and a capacitance level. Whenever the charging switch SW is turned on, the charging current source 10 charges the delay capacitor Cs so that a level of a level signal Ss of the delay capacitor Cs jumps to a higher level. Whenever the charging switch SW is turned off, the level of the level signal Ss is maintained. A discharging switch Q0 is connected in parallel with the delay capacitor Cs to discharge the delay capacitor Cs when receiving a reset signal Senx so that the level of the level signal Ss returns to zero. A chip area required by the oscillator 10 is large, thus increasing the cost for chip area. In addition, the waveform of the level signal Ss will generate a step to a higher level when the delay capacitor Cs is charged. During the process, small overshoots tend to occur. Additionally, the chip tends to have an electric leakage phenomenon at a high temperature, which hinders the rise of the level of the level signal Ss.
FIG. 3 depicts a traditional circuit schematic diagram of a current charging delay circuit. The charging current source 10 is connected to the driving voltage Vdd and the delay capacitor Cs and provides a current to charge the delay capacitor Cs so that the level signal Ss continues to rise over time. The discharging switch Q0 is connected in parallel with the delay capacitor Cs to discharge the delay capacitor Cs while receiving the reset signal Senx so as to allow the level of the level signal Ss returns to zero. In order to generate a longer delay by a current charging delay circuit, a smaller current and a larger capacitor are required. However, an electric leakage phenomenon of the chip will occur or become significant at a high temperature so that a smaller current cannot initiate the system easily. For example, the level signal Ss serves as a soft boot signal. In addition, a larger capacitor will increase the chip cost.
FIG. 4 depicts a circuit schematic diagram of a delay circuit disclosed in TW Patent I272611. A current source 22 is connected between a driving voltage Vdd and a node 24 to supply a current I. A current mirror 26 comprises a transistor M1 and a transistor M2. The transistor M1 generates a current I1. The transistor M2 mirrors the current I1 to generate a current I2. Hence, a relationship for current is: I=I1+I2. A capacitor C is connected between the node 24 and the transistor M1 of the current mirror 26. A switch SW1 is connected between the node 24 and ground. When the switch SW1 is turned on, the capacitor C discharges to return to zero. When the switch SW1 is turned off, a current that charges the capacitor C is the current I1. A voltage level shift circuit 28 is connected to the node 24 for correcting a level of a voltage VA at the node 24.
A size ratio of the transistor M1 to the transistor M2 in the current mirror 26 is 1:N. The current I2 is thus calculated to be I2=N*I1. With such a circuit structure, an equivalent capacitance value of the capacitor C becomes (N+1) times. In other words, when compared with the above-mentioned delay circuits, an electric capacity of the capacitor C in this structure only needs to be 1/(N+1) of that of the above-mentioned delay circuits to achieve the same effect. Hence, the chip area required by the capacitor is greatly reduced.
Although it is claimed the phenomenon that the system cannot be initiated due to electric leakages of the transistors would not occur in the delay circuit shown in FIG. 4, a theoretical analysis does not indicate this. An illustration is provided as follows:
First, since the size ratio of the transistor M1 to the transistor M2 is 1:N, it means that the transistor M2 would have a leakage current of N*IX if the transistor M1 has a leakage current of IX. If the leakage current N*IX of the transistor M2 is greater than the current I, that is the leakage current IX of the transistor M1 is greater than the current I1, the delay circuit still cannot be initiated normally. In brief, when the leakage capability of a single transistor (the transistor M1 has one transistor, the transistor M2 has N transistors) is greater than the charging current (I1=1/(N+1)) of the capacitor C, the delay circuit will fail.
Second, the transistor M1 is usually connected in parallel with a transistor switch. The existence of the transistor switch will affect the delay time, or even cause the delay circuit to fail.
For the forgoing reasons, there is a need for to solve the above-mentioned problems by providing a delay circuit.